Fabrication of trenches with multiple depths on the same substrate

ABSTRACT

Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches and for the shallow trenches at additional locations. Etching of the shallow and deep trenches then proceeds simultaneously.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to methods for fabricating integratedcircuits with trenches. More particularly, the present invention relatesto methods for forming trenches with multiple depths to isolate activedevice areas on SOI fabricated semiconductor wafers.

2. Description of the Related Art

Semiconductor wafer fabrication involves a series of processes used tocreate semiconductor devices and integrated circuits (ICs) in and on asemiconductor wafer surface. Fabrication typically involves the basicoperations of layering and patterning, together with others such asdoping, and heat treatments. Layering is an operation used to add thinlayers of material (typically insulator, semi-conductor or conductor) tothe surface of the semiconductor wafer. Patterning is an operation thatis used to remove specific portions of the top layer or layers on thewafer surface.

Conventional or bulk semiconductor devices are formed in semiconductormaterial by implanting a well of either P-type or N-type conductivity ina silicon substrate wafer of the opposite conductivity. Gates andsource/drain diffusions are then manufactured using commonly knownprocesses. These form devices known as metal-oxide-semiconductor (MOS)field effect transistors (FETs). When a given chip uses both P-type andN-type, it is known as a complimentary metal oxide semiconductor (CMOS).Each of these transistors must be electrically isolated from the othersin order to avoid shorting the circuits.

In order to deal with the junction capacitance and “off state” leakageproblem as well as obtain reduced size, semiconductor-on-insulatortechnology (SOI) has emerged. This technology constructs silicondevices, such as transistors, on a thin Si film formed on an insulativesubstrate rather than on a conventional silicon substrate.Silicon-on-insulator technology provides superior electrical isolationbetween adjacent components, reduces junction capacitance, and reducesthe power consumption.

SOI wafers may be formed in various ways including from a bulk siliconwafer by using conventional oxygen implantation techniques to create aburied oxide layer at a predetermined depth below the surface of thesilicon. The implanted oxygen oxidizes the silicon into insulatingsilicon dioxide in a normal distribution pattern centered at thepredetermined depth to form the buried oxide layer. MOSFET (metal oxidesemiconductor field effect transistors) transistors formed on SOIsubstrates also may be able to achieve higher speed operation withhigher drive currents, when compared with MOSFETs formed on conventionalbulk silicon substrates. One problem with forming field effecttransistors on an SOI wafer is the floating body effect. That is,isolation structures extending to the insulating layer prevent thevarious devices on the substrate from making contact with the body ofthe substrate.

Isolation structures, which are areas that prevent the active devicesfrom interfering with each other, are important for device operation. Avariety of techniques have been developed to isolate devices inintegrated circuits including shallow trench isolation (STI) andconventional LOCOS isolation. Shallow trench isolation (STI) is morepredominant for deep sub-micron technology, because it is free frombird's beak encroachment, field oxide thinning and leakage due to punchthrough.

In conventional CMOS technology shallow trenches are used to isolatedevices partially from each other while allowing the body contact to allthe devices. However, in SOI-CMOS technology the trench isolationcompletely separates devices from each other and does not permit a bodycontact. In order to partially implement and benefit from some of theSOI technology's advantages, deep trenches can be formed to completelyisolate some of the devices from the others (e.g., NMOS from PMOS),while a shallower trench is used for lateral isolation of the devicejunctions. This configuration still leaves a connection path to thedevice substrate and permits implementation of transistors on SOIsubstrate with a weak body tie.

Unfortunately, creation of two different trench depths on the samesubstrate is problematic. One conventional method creates two differenttrench depths for the above purpose by first patterning and etching onetrench depth in the substrate followed by another patterning and etchstep to define the second trench depth in the locations required forcomplete isolation. However, patterning the second trench after definingthe first trench is difficult, especially if the two trenches arecontiguous or overlap. Significant topography variation between thedepth of the first trench and the surface of the substrate makes resistcoverage difficult. The variation in the resist layer thus makeslithographic printing for the second trench difficult. Moreover,alignment between layers using alignment marks is very difficult whilefabricating dual trenches in this manner. The presence of thephotoresist interferes with alignment of the second layer relative tothe first layer because the non-planar resist diffracts the incominglight causing an apparent shift in the alignment mask position.

Unfortunately, there is no conventional process that is currentlyspecifically capable of overcoming the alignment and patterning issuesin a satisfactory manner. Accordingly, what is needed is an improvedprocess for formation of dual trench depths to completely isolate anindividual or a group of devices from others while allowing a partialbody contact to devices in SOI technology and which further providesinter layer alignment capabilities.

SUMMARY OF THE INVENTION

To achieve the foregoing, the present invention provides methods forfabrication of trenches with two or more depths on the same substrate. Astack having a pad oxide layer and a nitride (silicon nitride—Si₃N₄)layer is formed on the substrate. The wafer stack is covered with aresist layer and exposed with a first mask to form a preliminary trench.Using the mask, the preliminary trench is etched in the nitride film toa first depth corresponding to the location of the deep trenches and itsdepth corresponding to the difference in trench depth of the shallow anddeep trenches. A second photoresist layer is formed over the shallowtrench. A second mask is used to pattern the photoresist to correspondto the locations of the shallow and deep trenches. By forming thetrenches in this manner, dual depths of trench may be created on thesame wafer while minimizing the topography variations during processing.

In this approach, rather than etching one trench into the substratecompletely, only the depth difference between the two trenches is etchedinto the substrate in the deeper trench areas (or etching thecorresponding silicon nitride thickness equivalent to the etchdifference between the two trench depths in a silicon substrate). Byusing this approach, the overlapping of the areas with two differenttrench depths doesn't cause any significant etch problems. Moreover,lithography complications caused by the topography variations will bereduced significantly.

Thus, in accordance with various embodiments of the invention, trenchisolation is performed by forming an oxide layer on the surface of asemiconductor substrate, followed by deposition or formation of anitride layer. A preliminary trench is formed in the nitride layer byusing a first patterned photoresist mask, the depth of the preliminarytrench selected to correspond to the depth differential between theshallow and deep trenches formed in the final structure. A secondphotoresist mask is formed and used to extend the preliminary trench toa second depth (i.e., a deep trench) and to form shallow trenches (i.e.,a third trench) to a third depth in the substrate. The depth of thepreliminary trench is derived from the desired differential in depth ofthe second and third depth and the different etching rates in variousmaterials comprising the substrate.

According to another embodiment of the present invention, a removablealignment mark is formed from one or more of the preliminary trenches.This alignment mark is removed in a subsequent step by planarization inone embodiment, after completion of formation of shallow and deeptrenches.

According to yet another embodiment, a dual damascene interconnectstructure is formed by defining a preliminary via hole in a nitridelayer by using a first patterned photoresist mask, the depth of thepreliminary via hole selected to correspond to the depth differentialbetween the depth of the via and the depth of the trench formed in thefinal structure. A second photoresist mask is formed and used to extendthe via to a second depth (i.e., to contact an underlying metal line)and to form shallow trenches (i.e., a third trench) to a third depth inthe substrate. The depth of the preliminary trench is derived from thedesired differential in depth of the completed via and trench structureand the different etching rates in various materials comprising thesubstrate.

These and other features and advantages of the present invention aredescribed below with reference to the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Further advantages of the invention maybe obtained by reference to thedetailed description together with the figures. The figures provided arenot to scale so as to more clearly show details of the invention. Likereference numbers indicate like elements throughout the several views.

FIG. 1 is a diagrammatic cross-sectional view of a dual trench isolationstructure for SOI-MOS integrated circuit devices formed in accordancewith one embodiment of the present invention.

FIGS. 2A-2G are diagrams illustrating stages in the formation of a dualtrench isolation structure for SOI-MOS integrated circuit devices formedin accordance with one embodiment of the present invention.

FIGS. 3A-3C are diagrams illustrating steps in performing an etch ratecalculation in accordance with one embodiment of the present invention.

FIGS. 4A-4C are graphs illustrating experimental etch rates of thelayers depicted in FIGS. 2A-2G in accordance with one embodiment of thepresent invention.

FIGS. 5A-5E are diagrams illustrating stages in the formation of a dualdamascene interconnect structure in accordance with one embodiment ofthe present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Reference will now be made in detail to preferred embodiments of theinvention. Examples of the preferred embodiments are illustrated in theaccompanying drawings. While the invention will be described inconjunction with these preferred embodiments, it will be understood thatit is not intended to limit the invention to such preferred embodiments.On the contrary, it is intended to cover alternatives, modifications,and equivalents as may be included within the spirit and scope of theinvention as defined by the appended claims. In the followingdescription, numerous specific details are set forth in order to providea thorough understanding of the present invention. The present inventionmay be practiced without some or all of these specific details. In otherinstances, well known process operations have not been described indetail in order not to unnecessarily obscure the present invention.

This invention offers an approach to achieve multiple trench depths onthe same wafer by reducing the topography variations. In this approach,rather than etching one trench into the substrate completely, only thedepth difference between the two trenches is etched into the underlyinglayers in the deeper trench areas. In a preferred embodiment, theinitial or preliminary trench, for example, in the silicon nitride, isetched to a depth that is equivalent to the etch difference between thetwo trench depths in a silicon substrate. By using this approach, theoverlapping of the areas with two different trench depths do not causeany significant etch problems. Moreover, lithography complicationscaused by the topography variations will be reduced significantly.

FIG. 1 is a diagrammatic cross-sectional view of a dual trench isolationstructure for SOI-MOS integrated circuit devices formed in accordancewith one embodiment of the present invention. Embodiments of the presentinvention provide improved methods for forming dual trenches on asemiconductor substrate, such as the formation of the shallow trench 102and deep trenches 104 illustrated in FIG. 1. According to oneembodiment, the process may be used to form isolation trenches 102, 104positioned in a silicon-on-insulator substrate 108.

The isolation of devices formed on a semiconductor substrate has adirect effect on device reliability and basic transistorcharacteristics. Thus, effective device isolation techniques areimportant in the development of devices. Inadequate device isolationcauses leakage current and results in a loss of power supplied to asemiconductor chip. Inadequate isolation also increases the occurrenceof latch-up and causes temporary or permanent damage to the functions ofsemiconductor devices. It can also lead to degradation of a noisemargin, threshold voltage shift, and/or cross talk.

Shallow isolation trenches are typically used to provide isolation andare formed by a series of steps to etch and fill the trench. Forexample, according to conventional techniques, a semiconductor substrateis etched using a trench etch mask to form a trench. The trench is thenfilled with a chemical vapor deposition (CVD) layer to provide a deviceisolation layer. Next, the CVD layer is planarized and the trench etchmask is removed. But formation of both shallow and deep trenches isrequired to provide full and partial isolation when devices are formedon SOI substrates. It should be noted that the term shallow trench asused herein is generally in reference to a trench of lesser depth than adeep trench, for example, the shallow trench used in isolationstructures to provide partial isolation and the deep trench used toprovide full isolation. However, the invention is not limited toisolation structures and therefore the use of shallow and deep refers torelative depths and is not limited to isolation structures.

In the semiconductor structure 100 illustrated in FIG. 1, the deeptrenches 104 extend from the surface of the substrate 108 to theinsulator region 110, here the buried oxide layer. Hence, completeelectrical isolation is provided to separate the device defined bysource 112, drain 114, and gate 116 from adjacent devices (not shown).Further, the formation of shallow trench 102, extending from the surfaceof the substrate 108 to a depth above but short of the buried oxidelayer 110 enables a body contact 118 to form an electrical connection tothe substrate 108. As is known to those of skill in the relevant art,the buried oxide layer 110 may be formed by implanting an oxide layer ina silicon layer or by other means to provide an insulation layer 110between the device substrate 108 and the bulk silicon layer 120underlying the insulator layer 110.

The above-described conventional method for forming dual isolation issaddled with problems such as providing uniform resist coverage in thetrenches. That is, patterning the second trench after defining the firsttrench is difficult, especially if the two trenches are contiguous oroverlap. Significant topography variation between the depth of the firsttrench in the conventional method and the surface of the substrate makesthe resist coverage difficult and makes lithographic printing for thesecond trench difficult. The embodiments of the present invention solvethese problems by defining in a first step a preliminary trench having adepth corresponding to the difference in depths between the shallowtrench and the deep trench and then simultaneously forming the shallowtrench and extending the preliminary trench to form the deep trench.

Moreover, alignment problems are solved by using the preliminary trenchof the present invention for alignment of the second patterning mask.That is, using conventional methods, alignment of successive layers isvery difficult due to the depth of the shallow trenches into the siliconsubstrate. Embodiments of the present invention allow removablealignment targets for the second trench without degrading subsequentlayer alignment capability.

FIGS. 2A-2G are diagrams illustrating stages in the formation of a dualtrench isolation structure for SOI-MOS integrated circuit devices formedin accordance with one embodiment of the present invention. Thefabrication process begins, as shown in FIG. 2A, with the formation of athin pad oxide 202 layer on top of a silicon substrate 200 of a wafer201. The pad oxide 202 may be formed, for example, by thermal processingor in other ways well known to those of skill in the art, and may have athickness of about 50 to 500 Å.

Formation of the pad oxide 202 is followed by a nitride deposition toform a nitride layer 204. For example, the nitride deposition may beperformed using a LPCVD (low pressure chemical vapor deposition) processwhich results in deposition of about 300 to 10,000 Å, preferably about1000 to 2000 Å, of nitride 204 on top of the pad oxide layer 202.Photolithography techniques are used to transfer a pattern from areticle to the photoresist layer 205 to form a first mask 205 as shown.The nitride layer 204 is patterned and etched with the first mask 205 soformed, i.e., the “deep” trench mask, to form a preliminary trench 206,as illustrated in FIG. 2B.

Preferably, the preliminary trench 206 has a depth “Y” which is afunction of the difference in depths between the shallow trenches anddeep trenches to be formed in the silicon substrate 200. The preliminarytrench 206 may be formed in the open areas of the first photoresist mask205 preferably by etching using a high density plasma etch tool based-onHBr, O2, or Cl chemistry or any other similar chemistries. Thepreliminary trench depth Y may range from a minimal depth to nearly thefull depth of the nitride layer. This differential depth (“Y”) ispreferably determined by the difference in trench depth requirement ofthe completed shallow and deep trenches. This in turn is dependant uponthe etch rate selectivity between the nitride etch with respect to theunderlying pad oxide and silicon. In other words, the preliminary trench206 depth may be derived from the difference in trench depthrequirements between the shallow and deep trenches (e.g., requirementsrelating to electrical performance and isolation) and evaluating theetching chemistries selected and the layers to be etched by each. Thepreliminary trench depth so determined is the nitride equivalent to thetrench depth differential of the final shallow and deep trenchstructures in the silicon layer.

This step may also be used to create a sacrificial alignment mark 211for alignment of the shallow trench mask (i.e., “second” mask) in alater step. The sacrificial alignment mark 211, due to the use of thesame etch chemistry and its formation in the same etching step as thepreliminary trench 206, will have a depth about the same as the depth ofthe preliminary trench 206 but will not be “opened” during subsequentetching steps. Rather, the alignment mark will be protected by thesecond (i.e., shallow) patterned trench photoresist mask.

Next, as illustrated in FIG. 2C, the wafer is exposed with the “shallow”trench mask 212. This second mask 212 opens up other locations inaddition to the already partially etched deep trench areas, i.e., the“preliminary trenches”. That is, where the second mask opens uplocations coinciding with the preliminary trenches formed by the firstmask, i.e., the “deep” trench mask, a deep trench will be formed.Preferably, the shallow trench mask is aligned to the pattern formed bythe deep trench mask using the above fabricated alignment mark 211.Preliminary trenches 206 not “opened” by the “shallow” trench mask 212preferably will be used as alignment marks 211 and will later be removedentirely by the chemical-mechanical polishing or other planarizingoperation.

Alignment marks 211 are suitable for use in alignment of the second maskbecause they provide reflectivity for detection by optical detectors andmay be configured with patterns and widths optimized for suchapplication. That is, the alignment marks 211, having either nitride orpad oxide at the bottom of the preliminary trenches are sufficientlyreflective to function as alignment marks. Alignment is commonlyperformed using optical sensors sensitive to changes in topography orreflectivity. Hence, the exposed nitride or oxide surface issufficiently reflective to be used as a sacrificial alignment markaccording to embodiments of the present invention. In contrast,according to the above-described conventional method of forming dualdepth trenches, the shallow trench formed using a first mask extendsinto the silicon which provides insufficient reflectivity to be used asan alignment mark.

As illustrated in FIG. 2D, the “shallow” trench mask 212 is used to etchthe nitride layer 204 in a similar manner to the previous etch used toform the preliminary trenches 206. During this step, the preliminarytrenches designated for “deep” trench areas are etched further. Etchingprogresses such that the etching of the preliminary trenches 206 etchedinitially progresses to reach the pad-oxide layer 202 and subsequentlythe underlying silicon layer 200 long before the “shallow” trenchregions 218 reach the pad oxide 202 and silicon layers 200. Thus, the“head start” in etching depth provided by the preliminary trenches 206ultimately determines differential in trench depths between “deep” and“shallow” trenches 216 and 218. Once the trench in the shallow trenchlocations reaches the silicon layer 200, the nitride etch is preferablyswitched to a silicon etch, with selectivity to oxide, and continueduntil the desired shallow trench depth is achieved.

As illustrated in FIG. 2E, etching of the deep trench areas 216 willprogress simultaneously with the etching of the shallow trenches 218 inthe silicon layer 200 and stop on the bottom buried oxide layer 203.

Next, as illustrated in FIGS. 2F, the photoresist layer is removed. Atthis point an optional oxide liner step may be performed (not,shown)according to conventional methods known to those of skill in the art.That is, formation of the shallow and deep trenches 216 and 218 may befollowed by a liner oxidation of the trench sidewalls to form an oxideliner. For example, the oxide liner may be grown under oxygen in avertical furnace. The oxide thickness may vary from about 50 to 500 Ådepending on the technology requirements.

Next, as illustrated in FIG. 2F, the shallow and deep trenches 218 and216 (as well as the alignment mark 211) are filled with oxide 220, forexample, according to an HDP-CVD or APCVD oxide process known to thoseof skill in the art. The oxide filling enables completion of formationof shallow and deep isolation trenches. For example, an HDP-CVD processmay be employed to deposit 3000-8000 Å of oxide to completely fill thetrench prior to the CMP (chemical mechanical polishing) process.Alternatively, the trenches may be filled by other methods known tothose of skill in the relevant art.

Following oxide deposition, excess oxide 220 and the nitride layer 204are removed down to the substrate 200 level to form the stack asillustrated in FIG. 2G. This removal may be conducted, for example, by aCMP planarization down to the nitride layer which may subsequently beremoved by wet stripping such as by using hot phosphoric acid, accordingto procedures well known in the art.

Additionally, the surface of the substrate may be provided with a“sacrificial oxide” layer (not shown) that protects the underlyingsubstrate surface. Commonly, the sacrificial oxide layer is formed bythermally oxidizing the silicon of the substrate 200. Typically, thesacrificial oxide layer is formed to a thickness of about 100-150 Åthick.

At this stage, standard processing techniques may be used to completesemiconductor devices, for example, processing to form gate oxide layersand polysilicon gates. The processing described above allows for thedeep (i.e., full) trenches to be formed in an STI configuration betweendevices on a chip to provide complete isolation and the shallow (i.e.,partial) trenches to enable providing a body contact and to avoidproblems associated with floating body effects. As further illustratedin FIG. 2G, sacrificial alignment marks 211 have been removed by theprevious planarization procedures. Although the above isolation trenchexample contemplates use of a nitride layer over a pad oxide and siliconlayer, the invention is not limited to these layers or even etching intomultiple layers. The scope of the invention is intended to extend toetching trenches of dual depths into a single layer, such as where thepreliminary (first) trench and the following shallow and deep trenchesare all formed in a single layer.

FIGS. 3A-3C are diagrams illustrating steps in performing an etch ratecalculation in accordance with one embodiment of the present invention.Such an etch rate calculation is preferably used to determine thefeasibility of forming a preliminary trench of depth Y in the nitride toresult in a desired trench depth differential X in the final structure.Preferably, the depth Y of the preliminary trench 302 is determinedafter initially selecting a trench depth differential X to represent thedifference in trench depths between the shallow trench, such as trench102 illustrated in FIG. 1, and the deep trench, such as trench 104, alsoillustrated in FIG. 1.

FIG. 3A illustrates the first STI mask 302, the photoresist forming themask patterned to correspond to the location of the deep trench (seelocation 312 in FIG. 3C) and positioned over the nitride layer 304, padoxide layer 306, silicon substrate 308, and insulator region 310. FIG.3B illustrates the stack after the mask open etch and the subsequentformation of the second STI mask 303, i.e., for the shallow trenchlocations and further etching of the deep trench locations. Here Yrepresents the depth of the preliminary trench 311 etched into thenitride layer 304. For purposes of illustrating the etch trenchdifferential and the initial selected depth Y of the preliminary trench,“ER1” in the following calculations is taken to represent the Si₃N₄(silicon nitride) etch rate, for example, at 2300 Å/min. This same etchrate is assumed for calculation purposes in this example to representthe etch rate in the pad oxide layer. The etch rate in the silicon layer308 is represented by ER2, and assumed for calculation purposes here tobe 1100 Å/min. Thus, the relationship between X and Y for this examplecan be established by the following:X=Y*ER 2/ER 1Where ER1=2300 Å/min; ER2=1100 Å/min.To achieve X=500 Å, we need Y=1045 Å.

Thus, the foregoing relationship establishes that the trench depthdifferential is easily achievable using the materials and etchantsselected. By using the methods of the present embodiment, the topographyvariation seen by the second photoresist layer and mask is much lessthan in the conventional case. For example, the topography variationseen by (below) the shallow trench mask is only 1000 Å in the exampleillustrated compared to a topography variation of 2500 to 3500 Å or moreseen by conventional methods (i.e., the full depth of the conventionalshallow trenches).

As illustrated in FIG. 3C, the shallow trench 316 will break throughinto the silicon layer 308 when the depth of the deep trench 312 lies XÅ below the top surface of the silicon layer 308. This trench depthdifferential X will be maintained as both the shallow and deep trenchesare progressively etched into the silicon layer 308. In other words,since both the shallow and deep trenches are extended into the samematerial using the same etchant, the trench differential X will bemaintained as etching progresses through this common layer. Furtherrobustness is provided by the existence of the buried oxide layer 310 onthe SOI substrate. That is, the silicon etch will exhibit highselectivity between silicon and oxide and thus the buried oxide layer310 will essentially stop the etching of the deep trench 312, therebyavoiding the need for critical control over the etch times for the deeptrench. In a preferred embodiment, endpoint detection means are used todetermine the stopping point for the etches.

The foregoing example is intended to be illustrative and not limiting.The scope of the present invention is intended to extend to etchingtrenches of two or more different depths on a substrate, whether forisolation purposes, damascene interconnect structures, or otherwise.Furthermore, the etch rates described are illustrative only and also notintended to limit the invention to a particular etchant or materiallayer selection for etching.

According to the techniques of the present invention, the depth of thepreliminary trench is derived from the final depth differential desiredand by individually evaluating the effect of the common etchant on theprogression of each of the shallow and deep trenches. In situationswhere formation of the trenches takes place in only one material, thepreliminary trench depth is equivalent to the trench depth differentialbetween the shallow and deep trenches in the final structure. In oneembodiment, the preliminary trench depth may be set to the differentialdepth between the trenches also where the additional layers constitutingdifferent materials to be etched are thin or when the etching rates ofthe material layers to be etched do not differ appreciably from eachother. As illustrated above, once the deep trench progresses to thefinal silicon layer 308, the etching rate is reduced due to the factthat the etchant had been optimized to remove silicon nitride (and padoxide). The etchant selected for removal of the nitride layer in thetrenches preferably has a substantial non-zero etch rate in theunderlying (e.g. silicon) layer. Accordingly, the preliminary trenchdepth (and hence the initial differential between the bottom of theshallow and deep trenches) is reduced when the nitride etchant extendsthe deep trench into the silicon layer 308. This example is illustrativeand not intended to limit the scope of the invention. A preferredembodiment encompasses progressively selecting etchants optimized (i.e.,having higher removal rates for the selected layer as opposed to theother underlying layers) for each material layer encountered as theshallow trench progresses. The changeover to a new etchant preferablyoccurs when the shallow trench progresses into the underlying layer.This embodiment will usually result in the final trench differentialbeing less than the preliminary trench depth.

According to an alternative embodiment, the progression of the trenchescontinues, the etchant maybe optimized for the selective removal of thenext underlying layer as opposed to the current layer. For example, ifthe initial etch of the nitride layer is optimized for silicon asopposed to nitride, the preliminary trench depth will yield a greatertrench depth differential between the shallow and deep trenches in thefinal configuration (as compared to the preliminary trench depth) afterall etching is completed. Moreover, the scope of the present inventionis intended to extend to combinations of these techniques. That is, forexample, where multiple layers are being etched to form the trenches, insome cases the etchant may be optimized for the overlying layer and inother case for the underlying layer. The techniques of the presentinvention recognize that the initial trench depth differential (i.e.,the preliminary trench depth) may be modified at any time that a commonetchant is applied to both the shallow and deep trenches but therespective trenches are progressing through different materials. Thus,by evaluating the time intervals for the etchant and the differenttrench etch rates for the respective different materials, themodifications to the trench differential may be determined and theimpacts during each interval summed to yield the overall impact.

Using the guidance provided by the embodiments of the present invention,one skilled in the art could be expected, according to the methodsdescribed herein, to determine appropriate initial depths of trenchesfor formation of shallow and deep trenches of various dimension inlayers having various thicknesses, material compositions, and using avariety of etchant chemicals having different etching rates.

FIGS. 4A-4C are graphs illustrating experimental etch rates of layerssuch as those depicted in FIGS. 2A-2G in accordance with one embodimentof the present invention. As illustrated in FIGS. 4A and 4B, the etchrates of Si₃N₄ and oxides are similar, at 2303 and 2315 Angstroms/min.respectively using a recipe of 8 mTorr pressure, 500 W TCP RF power, 150W bottom RF power, 40 sccm of CHF₃ and 60 sccm of CF₄ process gas wasused in a LAM TCP9400PTX process chamber. The etch rate illustrated inFIG. 4C, using the same recipe, represents the silicon removal rate at1094 Angstroms/min., a rate of approximately 50% of the other materialremoval rates illustrated. Thus, the depth Y of the preliminary trenchesneeds to be approximately twice that of the desired differential depth(i.e., the differential between the shallow trenches and deep trenches)to achieve the desired dimension of the final structure.

Thus, according to the foregoing, trench isolation is performed byforming an oxide layer on the surface of a semiconductor substrate,followed by deposition or formation of a silicon nitride layer. Apreliminary trench is formed in the nitride layer, the depth of thepreliminary trench selected to correspond to the depth differentialbetween the shallow and deep trenches. A second mask such as a patternedphotoresist layer is then used for simultaneous formation of the deepand shallow trenches in the silicon (or other suitable underlyinglayer), although to different depths. The final depth of the shallow anddeep trenches is determined by the depth of the preliminary trench andthe etching rates in the silicon, nitride, and pad oxide layers in thisexample.

The process techniques described above enable the formation of a weakbody connection for electrical performance improvements when the dualdepth techniques are applied to the formation of isolation trenches onSOI substrates. That is, an efficient technique is provided for formingpartial (i.e., shallow) and full (i.e., deep) trenches to provide deviceisolation and a body tie on SOI substrates.

In describing the process techniques as applied to various substratelayers, dimensions have been provided as to the thickness of the layersas well as the various trenches formed. While preferable, thesedimensions are not intended to be limiting. Moreover, the materials inwhich the dual depth trenches of the present invention may be formed arenot particularly limited. For example, while not intending to belimiting, the process techniques may be applied to form dual trenchesfor dual damascene interconnect structures, such as formed in low-kinterconnect dielectrics. FIGS. 5A-5E illustrate the stages of forming adual damascene interconnect structure in accordance with one embodimentof the present invention. The process begins with a low-k interconnectlayer 504 formed over metal interconnect line 506 formed in dielectriclayer 508. Methods of forming low-k layers and other dielectric layersare known to those of skill in the art and therefore further descriptionis deemed unnecessary here. Low-k interconnects according toconventional methods are provided often with capping layers, such assilicon nitride or silicon carbide layer 502 illustrated. Photoresistlayer 510 is shown patterned for providing a mask open area to form apreliminary trench (i.e., via). As illustrated in FIG. 5B, thepreliminary trench 512 is etched into the nitride layer to a depthcorresponding to the difference in depths between the trench and via inthe final configuration. As illustrated in FIG. 5C, the trench mask 520is formed to define the location of the trench relative to the alreadyformed via 512. Etching of the remaining thickness of the nitride layer502 and the low-k layer 504 then proceeds to simultaneously form thetrench and via The bottom of the via is stopped on the barrier layer511. Finally, as illustrated in FIG. 5D, a barrier open etch isperformed to expose the metal line 506. Conventional copper barrierlayer deposition and copper fill steps follow to form the dual damasceneinterconnect structure in accordance with conventional techniques. Byusing the guidance provided by the description herein as applied to dualdepth isolation layers, the initial depth of the via 512 formed in thenitride layer maybe selected to correspond to the final differences indepths of the trench and via (e.g., relative to the top surface of thelow-k layer 504) and thus to form the dual damascene interconnectstructure by the novel method described.

Although the foregoing invention has been described in some detail forpurposes of clarity of understanding, it will be apparent that certainchanges and modifications may be practiced within the scope of theappended claims. For example, the invention has generally been describedin relation to the formation of dual trenches in a substrate. The dualtrenches are intended to be illustrative and not limiting. That is, thescope and spirit of the invention is intended to extend to multipletrenches using the guidance provided in the specification. For example,fabrication of trenches having three or more depths in the samesubstrate may be completed by defining the first two (“dual”) trenchesas described above and extending the first two trenches in the step whenthe third trench is defined using a third mask. This methodology maylikewise be extended beyond three depths for the trenches to any numberof multiple depths. Accordingly, the present embodiments are to beconsidered as illustrative and not restrictive, and the invention is notto be limited to the details given herein, but may be modified withinthe scope and equivalents of the appended claims.

1. A method of forming an isolation structure on an integrated circuitsubstrate, comprising: providing a substrate configured so that itincludes: a silicon layer that overlies a buried oxide layer; a padoxide layer overlying the silicon layer; and a nitride layer overlyingthe pad oxide layer; forming a first pattern mask over the substratesuch that a first pattern of apertures is formed the first pattern mask;first etching of the nitride layer through apertures defined by thefirst pattern mask to form a fist set of trenches in the nitride layerhaving a first depth; removing the first pattern mask; forming a secondpattern mask over the substrate that defines a second pattern ofapertures in the second pattern mask; second etching of the of thesubstrate through the apertures defined by the second pattern mask toform a second set of trenches of a second depth in the substrate and toextend the depth of exposed portions of the first set of trenches to athird depth; and third etching of the of the substrate through theapertures defined by the second pattern mask to form to extend thedepths of the second set of trenches to a fourth depth and to furtherextend the depth of exposed portions of the second set of trenches.
 2. Amethod of claim 1 further comprising: removing the second pattern mask;and filling the openings caused by the first, second, and third etching.3. A method of claim 1, wherein at least a portion of the apertures ofthe second pattern mask are not in alignment with the apertures of thefirst pattern mask.
 4. A method of claim 1, wherein filling the openingscaused by the first and second etching comprises filling the openingswith an electrically insulating material.
 5. A method of claim 1,wherein said providing of the substrate includes providing a substratehaving a conductive interconnect structure that lies under the buriedoxide layer; and wherein the third etching of the of the substratecomprises further extending the depth of exposed portions of the secondset of trenches until said trenches extend through the buried oxidelayer to expose the conductive interconnect structure.
 6. A method ofclaim 1, wherein said providing of the substrate includes providing asubstrate having a conductive interconnect structure that lies under theburied oxide layer; and wherein the third etching of the of thesubstrate comprises further extending the depth of exposed portions ofthe second set of trenches until said trenches extend trough the buriedoxide layer to expose the conductive interconnect structure.
 7. A methodof claim 6 further comprising: removing the second pattern mask; andfilling the trenches that extend through the buried oxide layer toexpose the conductive interconnect structure with conductive material toenable electrical connection with the conductive interconnect structure.8. A method of claim 1, wherein said second etching of the of thesubstrate is accomplished using a first etchant; and said third etchingof the of the substrate is accomplished using a second etchant.
 9. Amethod of claim 8, wherein said first etchant has good etch selectivityfor silicon nitride; and wherein said second etchant has good etchselectivity for silicon.
 10. A method of claim 9, wherein the secondetching of the of the substrate proceeds until at least a portion of padoxide layer is reached; and wherein the third etching of the of thesubstrate proceeds until at least a portion of buried oxide layer isreached.